1. Technical Field
The disclosed embodiments relate to multi-modulus dividers (MMDs).
2. Background Information
The receiver and transmitter circuitry within a cellular telephone typically includes one or more local oscillators. Such a local oscillator may, for example, include a phase-locked loop (PLL) that receives a stable but relatively low frequency signal (for example, 20 MHz) from a crystal oscillator and generates the output signal of the selected relatively high frequency (for example, 900 MHz). The feedback loop of the PLL includes a frequency divider that receives the high frequency signal and divides it down to obtain a low frequency signal that is of the same phase and frequency as the signal from the crystal oscillator.
A type of divider referred to here a “multi-modulus divider” (MMD) is often used to realize the frequency divider. The MMD receives the high frequency input signal SIN and divides it by a divisor value DV to generate the low frequency output signal SOUT. The MMD includes a plurality of modulus divider stages (MDSs) that are chained together to form the MMD. Each MDS (except the last MDS) receives a feedback modulus control signal from the next MDS in the chain. Each MDS also receives a modulus divisor control signal S. If the modulus divisor control signal S for a particular MDS has a first digital logic value then the MDS operates in a divide-by-two mode, otherwise the MDS operates in a divide-by-three mode. The modulus divisor control signal values S of the various MDS stages of the MMD together determine the divisor value DV by which the MMD divides.
In many MMD applications, the MMD output signal is to have a duty cycle of approximately fifty percent. The output signal is also to have low jitter with respect to the high frequency MMD input signal. Each MDS stage introduces an amount of jitter. Due to the cascading of the MDS stages, the jitter of the various MDS stages of the MMD accumulates. In one cellular telephone application involving a cellular telephone standard, using the output of the last MDS as the MMD output results in so much accumulated jitter that the noise requirement imposed on the MMD by the cellular telephone standard cannot be satisfied.
One conventional way to solve this problem is to use the jitter-free high frequency MMD input signal to synchronize (to “reclock”) the jittery low frequency MMD output signal with a high speed flip-flop. This makes the output of the flip-flop almost jitter free. This solution, however, generally requires a well-defined phase relationship between the high frequency MMD input signal and the low frequency MMD output signal. Due to the MMD architecture, it may be difficult to maintain an adequately constant phase relationship between the two signals when the divisor value DV is large.
A second conventional way to solve the jitter problem involves three flip-flops. The first flip-flop synchronizes the modulus control signal that controls the first MDS stage with the high frequency MMD input signal. The modulus control signal is the signal that determines whether the first MDS stage divides by two or divides by three. The synchronized output of the first flip-flop is supplied to the clock input of the second flip-flop. The D-input of the second flip-flop is coupled to receive a fixed digital logic high value so that an edge of the synchronized output of the first flip-flop clocks the digital logic high value into the second flip-flop. The reset input of the second flip-flop is coupled to receive a reset signal that is a logical combination of several signals output from several of the MDSs in the middle of the MMD. The reset signal therefore resets the second flip-flop to a digital logic low. The output of the second flip-flop is supplied to the D-input of the third flip-flop and the third flip-flop is clocked using the high frequency MMD input signal so as to synchronize the output of the second flip-flop with the high frequency MMD input signal. The reset input of the third flip-flop is coupled to receive the reset signal. The Q output of the third flip-flop outputs the desired low-jitter low frequency signal that has a duty cycle of approximately fifty percent. Unfortunately, this second conventional solution consumes a large amount of power because two of the three flip-flops are being clocked by the high frequency MMD input signal. Power consumption is therefore undesirably high.